Intel’s U.S. Advanced Packaging Enables Next-Generation AI Semiconductors

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As AI demands unprecedented "brain power," the semiconductor industry is moving past the era of relying on single, massive chips. Advanced packaging is the essential craft of interconnecting multiple specialized chips together. This allows them to function as a single, powerful unit that runs faster handling the massive workloads of the future.

Intel’s been doing advanced chip packaging for years in the U.S. and across the globe. It’s one of the most crucial parts of creating multi-chip packages for today’s technology products.

Inside Intel's Rio Rancho, New Mexico facilities, advanced packaging technologies are expanding the "reticle limit"—scaling packages to 8x the industry standard today, and over 12x by 2028.

We’ve moved past the era of one big chip to a system of chips, almost like a “silicon mosaic”, where specialized tiles are interconnected in a single, massive package.

“Back in the 1980s this site was the leader in 6-inch wafer manufacturing. Now over 40 years later, things have flipped and this site is the leader in the United States for advanced packaging,” explains Katie Prouty, manager of Intel’s Fab 9 advanced packaging facility in New Mexico.

To meet the massive demands of AI, Intel is pushing the boundaries of what’s physically possible. Intel Foundry is building up with Foveros stacking, and across with EMIB interconnects.

“Some of the customers are coming to us first for advanced packaging,” Prouty says. “When we’re successful delivering to those customers, they’ll continue to grow their trust and faith in Intel as a foundry.”

What started in Rio Rancho, New Mexico as 25 employees in 1980, has now proudly grown to 2,700 employees and 500 suppliers bringing critical U.S. advanced packaging technology to market.

One of the advanced packaging processes happening at Intel New Mexico’s Fab 9 focuses on connecting smaller specialized chip tiles, or chiplets, into a single, high-performance system. A technology called Foveros allows Intel Foundry to connect these chiplets on a silicon interposer. It is easiest to think of that interposer like a pizza crust.

“Inside the fab, the chip attach tool is the first step in Intel’s Foveros advanced packaging process,” says Chris Seibert, Principal Engineer at New Mexico’s Fab 9. “If we use a food analogy, this is the tool that brings in a ‘pizza crust’, or silicon wafer, and whatever ‘pizza toppings’ or specialized chiplets you want, we feed into the other side of this machine, and it attaches them to the top of that ‘crust’.”

Then it travels to a different tool that acts as a literal oven to bake that system together. Once it comes out, the overhead robot track system of FOUPs (front-opening unified pods) bring the wafer to another machine where epoxy fills in under and around those chiplets to make sure everything is pressed together.

Finally, the wafers are diced into individual packages in another tool using water-cooled blades for precision. “The great part about that process is it lets us take a bunch of different chips from different designs or different technology nodes and put them all together onto one wafer,” Seibert says.

Using Foveros technology, individual chiplets function as a single, powerful unit that runs faster while handling massive workloads. Foveros helps laptop batteries last longer by placing power-hungry circuits on more power efficient process nodes. Laptops can become thinner, and edge computing devices can fit into smaller spaces without sacrificing performance. Foveros also allows for more features to be packed into a smaller footprint, from the factory floor to your desk.

Part of the advanced packaging process of semiconductors includes a technology called EMIB (Embedded Multi-die Interconnect Bridge), where specialized chips are linked together on a package with tiny silicon bridges embedded in the substrate. This approach allows different chips to work as a single unit, providing the massive power needed for AI while improving efficiency and reducing manufacturing costs.